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First-ever technology to control harmful oxidation in III-V semiconductors for unprecedented performance

III-V semiconductor surfaces exhibit high defect state densities due to the harmful native oxides that form as soon as the material is exposed to air.  This leads to drastic deterioration of the device performance.

Thanks to the extensive expertise in semiconductor surface engineering, our team has developed a breakthrough technology to address the problem of native oxidation in compound semiconductor materials.

 

We have prices, atomic-level control over the oxidation so that the resulting surface is extremely high-quality and more resistant to further oxidation. We can promote surface crystalline oxide reconstructions in III-V semiconductors for the first time. 

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Untreated semiconductor surface exhibits a large number of oxidation-induced defects

 

These atomic-level defects are ultimately an amorphous oxide and contaminations on top of the III-V crystal. This native oxide is naturally characterized by atomic-level bond disorder, dangling bonds, and mixed group III and group V oxides

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Scanning Tunneling Microscope (STM) images of III-V native oxide surface layer (left) and  crystalline oxide reconstruction developed by Comptek Solutions (right)

With Kontrox, the efficiency and performance of compound semiconductor devices are taken to record levels while manufacturing costs are significantly reduced.

Novel crystalline structures formed with Kontrox are thermodynamically stable and are characterized by unprecedentedly low levels of surface state densities. Additionally, Kontrox helps to avoid the oxidation of the materials during the subsequent manufacturing phases reducing the risk of defective parts and improving the manufacturing yields.

Scope of applicability

Kontrox provides high-quality passivation in a wide range of III-V semiconductor materials and device types. The technology is ready for commercialization for the materials listed below.  However, technology applicability extends beyond those, and we are available for implementation studies for other III-V materials and device types.

Contact us for more information.

Optoelectronics

• Mesa sidewall passivation

• Barrier layer in QW stack

• Facet passivation

CMOS

• Key enabler for III-V MOS based transistors for gate dielectric interface passivation

RF & Power Electronics

• Interface passivation layer for MOS-HEMT

Laser diodes

LED

CPV

IR detectors

MOS III-V

p-HEMT

m-HEMT

GaN

GaAs

AIGaAs

InAlGaAs

InGaAs

InP

GalnP

AlGaInP

GaN

AIGaN

InGaN

GaAs

AlGaP

AIGaInP

GaP

AIInP
GalnP
GaInNAsSb
GaAs
InGaAs
AlGaInP
AlGaAs

GaAs
InGaAs
InSb
InP
GaSb

InAs
InGaAs
InSb

InP
InGaAs
GaInP

GaN
AlGaN
InGaN

GaAs
AIGaAs
GaInP
InGaAs