Improving Quality of

Gate Dielectric Interface 

Semiconductor-dielectric interfaces are the key for many modern semiconductor device operations and the quality of this crucial interface basically determines the device performance in many applications. In transistors using compound semiconductor materials achieving these levels of quality is extremely difficult.

​The issue is due to the very aggressive oxidation of surfaces during device manufacturing and the following high density of interface defects states which diminishes the device performance. Generally, dielectric materials are some kind of oxide, such as  Al2O3, HfO2 grown via i.e Atomic Layer Deposition (ALD). These oxides introduce a pathway for the oxidation of the III-V semiconductor surface. It is well known the  “self-cleaning” effects of ALD processes for III-V surfaces, however, the III-V- ALD Oxide interface has been still characterized by a high density of interface states that are impeding the realization of III-V based CMOS technology or high-quality metal-insulator enhancement-mode high-electron-mobility transistors (MIS-HEMTs) for radio-frequency and power electronic applications.

​Kontrox resolves the issue by forming natural perfect quality crystalline III-V oxide structures that passivate and protect the surfaces against oxidation prior to the deposition of dielectric material, ensuring the highest quality interfaces. Kontrox layers are thermodynamically stable and in addition, to reduce the interface states it also increases the barrier height at the surface behaving as a natural diffusion barrier for further oxidation.



Photoluminescence improvement at the interfaces of

1. ALD Al2 O3 /InP

2. ALD Al2 O3 /GaAs 

​The passivation effect has been demonstrated by producing III-V MIS capacitors yielding an even 98% reduction of defect state densities at the III-V ALD-grown dielectric interface. The improved interfaces can be verified by dramatic enhancement in the photoluminescence intensity which is an indication of reduced defect-related non-radiative recombination. The applicability of the improved III-V dielectric interfaces is most evident in transistor-based applications where good quality channel modulation and minimized gate leakage is essential.

Enhancement mode HEMTs 

The increasing popularity and adoption of high-speed networks such as 5G and IoT have significantly impacted the demand for high performing RF components. The seemingly unlimited demand for high-speed wireless data transfer places enormous new requirements on chip- and transistor-level performance. For the semiconductor industry, in particular, that means higher efficiency combined with higher operating frequency of individual transistors in the RF chips. At the same time, the market is demanding a reduction of die-size and reduced cost of individual chips. Also, as the frequency space gets more crowded, the industry is challenged to keep the signals distinct with high signal to noise ratio.

High Electron Mobility Transistors (HEMT) are common key individual components in RF applications and power electronics. They are normally fabricated with GaAs, InP or GaN based technologies. However, need for negative voltages and high static power consumption in the D-mode devices has led to the development of normally-off enhancement mode (E-mode) HEMT transistors.

The III-V based E-mode transistors have been suffering from high gate leakage at forward gate bias due to low Schottky barrier height limits the input dynamic range and increase the noise figure. This has straight implication to e.g. the power-added-efficiency (PAE) of the transistor and, eventually, to the performance of the power amplifier itself. To restrain the gate leakage in the E-mode devices the industry is adopting a metal-insulator-semiconductor (MIS) type of structures most familiar from the silicon industry. However, unlike silicon-insulator system, the III-V-insulator stack suffers from very poor interface quality which act also as a pathway for the forward bias gate leakage preventing efficient E-mode operation.


Kontrox yields the best interface quality at the gate dielectric/III-V interface minimizing the forward bias leakage and allowing efficient E-mode operation both for GaAs and AlGaN/GaN based HEMT technologies for RF and Power Electronics applications.  

Key Enabler for III-V CMOS

Silicon related digital transistor technology has been dominating the IC industry for several decades. However, the geometrical transistor scaling as per the Moore’s law, is facing its fundamental limits as the smallest dimensions in the chips are soon at the atomic level. It is generally accepted that Moore’s law cannot continue without new solutions and innovations in the front-end-of-line (FEOL) device architectures. This includes introducing new materials of which the III-V compound semiconductors are the main candidates for substituting silicon. The main reason is even order of magnitude higher carrier mobilities compared to silicon allowing higher operating frequencies at equivalent chip dimensions compared to silicon.

One of the biggest obstacles in realizing III-V based digital CMOS technology has been the poor quality III-V gate dielectric interface which leads to Fermi-level pinning, trap assisted parasitic tunneling, increased sub-threshold swing and poor channel modulation. Kontrox technology is the key enabler for the low defect level interfaces allowing minimized gate leakage, un-pinned Fermi-level and enhanced channel modulation for the next generation transistor technologies.

 © 2021 by Comptek Solutions.  

Comptek Solutions Oy

Voimakatu 14, 20520 TURKU, Finland

tel: +358 442404004

Reg. number: 2815285-8

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